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SN74GTL2014PWR Scheda tecnica(PDF) 4 Page - Texas Instruments |
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SN74GTL2014PWR Scheda tecnica(HTML) 4 Page - Texas Instruments |
4 / 20 page SN74GTL2014 SCLS746A – FEBRUARY 2014 – REVISED OCTOBER 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings Specified at TA = –40°C to 85°C unless otherwise noted (1) MIN MAX UNIT VCC Supply voltage –0.5 4.6 V IIK Input clamping current, VI < 0 V –50 mA VSEL Input control voltages SEL(2)(3) –0.5 6 V A port –0.5 7 VI Input voltage V B port –0.5 4.6 IOK Control input clamp current, VO < 0 V –50 mA A port –0.5 7 VO Output voltage V B port –0.5 4.6 A port 40 IOL Current into any output in the low state mA B port 80 IOH Current into any output in the high state –40 mA (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to ground, unless otherwise specified (3) VI and VO are used to denote specific conditions for VI/O 6.2 Handling Ratings MIN MAX UNIT Tstg Storage temperature range –55 150 °C Human Body Model (HBM), JEDEC: JESD22-A114(2) All pins 0 2 VESD (1) kV IEC61000-4-2 contact discharge(3) All pins 0 1 (1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by assembly line electrostatic discharges into the device. (2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance. (3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN NOM MAX UNIT VCC Supply voltage 3 3.3 3.6 V GTL– 0.85 0.9 0.95 VTT Termination voltage GTL 1.14 1.2 1.26 V GTL+ 1.35 1.5 1.65 Overall 0.5 2 / 3 VTT VCC / 2 GTL– 0.5 0.6 0.63 VREF Reference voltage V GTL 0.76 0.8 0.84 GTL+ 0.87 1 1.1 A port 0 3.3 5.5(2) VI Input voltage V B port 0 VTT 3.6 A port and DIR 2 VIH High-level input voltage V B port VREF + 50 mV (1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. (2) The VI(max) of LVTTL port is 3.6 V if configured as output (DIR=L) 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: SN74GTL2014 |
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