SN74CBTLV3857

LOW VOLTAGE 10BIT FET BUS SWITCH

WITH INTERNAL PULLDOWN RESISTORS

SCDS085E − OCTOBER 1998 − REVISED OCTOBER 2003

4

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

VDDQ/2

VDDQ/2

VREF†

VREF†

VOH

VOL

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

500

Ω

500

Ω

Output

Control

Output

Waveform 1

S1 at 2

× VDDQ

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

VIL (AC)§

VOL + 0.15 V

VOH − 0.15 V

0 V

VIH (AC)‡

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

VDDQ × 2

GND

TEST

S1

† VREF = 0.38 × VCC

‡ VIH(AC) = VREF + 350 mV

§ VIL(AC) = VREF − 350 mV

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

tPHL

VDDQ/2

VDDQ/2

VDDQ

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VDDQ/2

VDDQ/2

tPLH

VDDQ × 2

VDDQ

Figure 1. Load Circuit and Voltage Waveforms