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74AVC16334DGGRG4 Scheda tecnica(PDF) 10 Page - Texas Instruments |
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74AVC16334DGGRG4 Scheda tecnica(HTML) 10 Page - Texas Instruments |
10 / 16 page www.ti.com PARAMETER MEASUREMENT INFORMATION VOH VOL th tsu From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT S1 2 × VCC Open GND 500 Ω 500 Ω tPLH tPHL Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ VCC 0 V VOH VOL 0 V VOL + 0.3 V VOH − 0.3 V 0 V VCC 0 V 0 V VCC 0 V tw Input VCC VCC VCC VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Output Input tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 SN74AVC16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES154I – DECEMBER 1998 – REVISED MAY 2005 V CC = 3.3 V ± 0.3 V Figure 5. Load Circuit and Voltage Waveforms 10 |
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