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SN74AUP1G08DRLR Scheda tecnica(PDF) 4 Page - Texas Instruments |
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SN74AUP1G08DRLR Scheda tecnica(HTML) 4 Page - Texas Instruments |
4 / 38 page 1 B 2 A 4 Y 5 V Not to scale 3 GND CC 1 2 A B C Not to scale A V B GND Y CC Not to scale 1 A 6 V 2 B 5 N.C. 3 GND 4 Y CC 1 2 A B C Not to scale A V B DNU GND Y CC Not to scale 1 A 2 B 3 GND 4 Y 5 VCC 4 SN74AUP1G08 SCES502P – NOVEMBER 2003 – REVISED JUNE 2016 www.ti.com Product Folder Links: SN74AUP1G08 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated 5 Pin Configuration and Functions DRL, DCK, or DBV Packages 5-Pin SOT, SC70, or SOT-23 Top View DRY or DSF Packages 6-Pin SON Top View N.C. – No internal connection DPW Package 5-PIN X2SON Top View See mechanical drawings for dimensions. YFP Package 6-Pin DSBGA Top View DNU – Do not use YZP Package 5-Pin DSBGA Top View |
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