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SN74AUP1G02DSFR Scheda tecnica(PDF) 11 Page - Texas Instruments

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Il numero della parte SN74AUP1G02DSFR
Spiegazioni elettronici  Low-Power Single 2-Input Positive-NOR Gate
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SN74AUP1G02
www.ti.com
SCES568H –JUNE 2004–REVISED OCTOBER 2014
9 Detailed Description
9.1 Overview
The SN74LVC1G02 device contains one 2-input positive-NOR gate and performs the Boolean function Y = A + B
or Y = A × B.
The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW
package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square
footprint saves significant board space over other package options while still retaining the traditional
manufacturing friendly lead pitch of 0.5 mm.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered. The Ioff feature also allows for live
insertion.
9.2 Functional Block Diagram
9.3 Feature Description
• Wide operating VCC range of 0.8 V to 3.6 V
• 3.6-V I/O tolerant to support down translation
• Input hysteresis allows slow input transition and better switching noise immunity at the input
• Ioff feature allows voltages on the inputs and outputs when VCC is 0 V
• Low noise due to slower edge rates
9.4 Device Functional Modes
Table 1. Function Table
INPUTS
OUTPUT
Y
A
B
L
L
H
L
H
L
H
L
L
H
H
L
Copyright © 2004–2014, Texas Instruments Incorporated
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