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74ALVCHG162280GRG4 Scheda tecnica(PDF) 1 Page - Texas Instruments

Il numero della parte 74ALVCHG162280GRG4
Spiegazioni elettronici  16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

74ALVCHG162280GRG4 Scheda tecnica(HTML) 1 Page - Texas Instruments

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VCC
GND
2B7
1B7
2B6
GND
1B6
2B5
1B5
VCC
2B4
1B4
2B3
1B3
GND
2B2
1B2
2B1
1B1
VCC
GND
2D2
1D2
2D1
1D1
VCC
C1
C2
A1
GND
A2
A3
A4
VCC
A5
A6
A7
GND
CLK
SEL
VCC
GND
1B8
2B8
1B9
GND
2B9
1B10
2B10
VCC
1B11
2B11
1B12
2B12
GND
1B13
2B13
1B14
2B14
VCC
GND
1B15
2B15
1B16
2B16
VCC
A16
A15
A14
GND
A13
A12
A11
VCC
A10
A9
A8
GND
OE
DIR
DBB PACKAGE
(TOP VIEW)
xxxx
SN74ALVCHG162280
16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
WITH BYTE MASKS AND 3-STATE OUTPUTS
SCES093D – FEBRUARY 1997 – REVISED OCTOBER 2004
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Sub-Micron Process
A-Port Outputs Have Equivalent 50-
Ω Series
Resistors and B-Port Outputs Have Equivalent
20-
Ω Series Resistors, So No External
Resistors Are Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Packaged in Thin Very Small-Outline Package
NOTE: For order entry, the DBB package is abbreviated to G. For
tape and reel, the DBBR package is abbreviated to GR.
The SN74ALVCHG162280 is a 16-bit to 32-bit
registered bus exchanger. This device is intended for
use in applications where data must be transferred
from
a
narrow
high-speed
bus
to
a
wide
lower-frequency bus. It is designed specifically for
low-voltage (3.3-V) VCC operation.
The device provides synchronous data exchange
between the two ports, A and B. Data is stored in the
internal registers on the low-to-high transition of the
clock (CLK) input. For data transfer in the B-to-A
direction, the select (SEL) input selects 1B or 2B data
for the A outputs.
For data transfer in the A-to-B direction, a two-stage
pipeline is provided in the 1B path, with a single
storage register in the 2B path. Data flow is controlled
by
the
active-low
output-enable
(OE)
and
direction-control (DIR) inputs. DIR is registered to
synchronize the bus direction changes with the clock.
Two mask bits are provided for both data bytes. The
data (D) outputs are controlled by OE.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1997–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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