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SN74ABT162823DGGR Scheda tecnica(PDF) 6 Page - Texas Instruments |
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SN74ABT162823DGGR Scheda tecnica(HTML) 6 Page - Texas Instruments |
6 / 9 page SN54ABT162823, SN74ABT162823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS473B – JUNE 1994 – REVISED JANUARY 1997 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C SN54ABT162823 SN74ABT162823 UNIT MIN MAX MIN MAX MIN MAX fclock Clock frequency 0 150 0 150 0 150 MHz t Pulse duration CLR low 3.3 3.3 3.3 ns tw Pulse duration CLK high or low 3.3 3.3 3.3 ns CLR inactive 1.6 2 1.6 tsu Setup time before CLK ↑ Data 1.7 1.7 1.7 ns CLKEN low 2.8 2.8 2.8 th Hold time after CLK ↑ Data 1.2 1.2 1.2 ns th Hold time after CLK ↑ CLKEN low 0.6 0.6 0.6 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C SN54ABT162823 SN74ABT162823 UNIT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX fmax 150 150 150 MHz tPLH CLK Q 2.3 4.6 6.2 2.3 8.4 2.3 7.5 ns tPHL CLK Q 2.8 4.6 6.1 2.8 7.1 2.8 6.7 ns tPHL CLR Q 2.8 5 6.2 2.8 7.2 2.8 7 ns tPZH OE Q 1.7 3.8 4.9 1.7 5.8 1.7 5.6 ns tPZL OE Q 3 5 6.1 3 7.2 3 7 ns tPHZ OE Q 2.7 4.8 6.1 2.7 7.3 2.7 6.6 ns tPLZ OE Q 1.9 4.6 6.7 1.9 10.2 1.9 9 ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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