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LM3407 Scheda tecnica(PDF) 11 Page - Texas Instruments |
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LM3407 Scheda tecnica(HTML) 11 Page - Texas Instruments |
11 / 22 page VISNS VMSL 0 D/fSW 1/fSW VRP VREF 0 + - Error Amplifier D/fSW 1/fSW PWM signal Generator D/fSW 1/fSW VPWM 0 T PWM sawtooth To power switch VISNS1 VMSL 0 VISNS2 VMSL 0 VPWM 0 LM3407 www.ti.com SNVS553B – JANUARY 2008 – REVISED MAY 2013 Figure 21. Pulse-Level Transformation When VMSL is higher than VREF, the peak value of VRP, the switching duty cycle of the power switch will be reduced to lower VMSL. When VMSL is lower than the peak value of VRP, the switching duty cycle of the power switch will be increased to raise VMSL. For example, when IOUT is decreased, VMSL will become lower than VREF. In order to maintain output current regulation, the switching duty cycle of the power switch will be increased and eventually push up VMSL until VMSL equals VREF. Since in typical floating buck regulators VMSL is equal to IOUT * RISNS, true average output current regulation can be achieved by regulating VMSL. Figure 23 shows the waveforms of VISNS and VRP under closed loop operation. Figure 22. Implementation of the PWM Switching Signal Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM3407 |
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