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SN74HC193PWG4 Scheda tecnica(PDF) 4 Page - Texas Instruments |
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SN74HC193PWG4 Scheda tecnica(HTML) 4 Page - Texas Instruments |
4 / 21 page SN54HC193, SN74HC193 4BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR) SCLS122D − DECEMBER 1982 − REVISED OCTOBER 2003 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 typical clear, load, and count sequence The following sequence is illustrated below: 1. Clear outputs to 0 2. Load (preset) to binary 13 3. Count up to 14, 15, carry, 0, 1, and 2 4. Count down to 1, 0, borrow, 15, 14, and 13 Data Inputs Data Outputs LOAD A B C D UP CO QA QB QC QD Clear Count Up 013 14 0 1 2 BO Count Down 15 14 13 DOWN CLR 15 1 0 Preset NOTES: A. CLR overrides LOAD, data, and count inputs. B. When counting up, count-down input must be high; when counting down, count-up input must be high. |
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