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SM320F28335GBS Scheda tecnica(PDF) 6 Page - Texas Instruments

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Il numero della parte SM320F28335GBS
Spiegazioni elettronici  Digital Signal Controller (DSC)
Download  182 Pages
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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SM320F28335GBS Scheda tecnica(HTML) 6 Page - Texas Instruments

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SM320F28335-HT
SPRS682E – DECEMBER 2010 – REVISED JANUARY 2014
www.ti.com
6-12
General-Purpose Output Timing
.............................................................................................. 127
6-13
Sampling Mode
................................................................................................................. 127
6-14
General-Purpose Input Timing
................................................................................................ 128
6-15
IDLE Entry and Exit Timing
.................................................................................................... 129
6-16
STANDBY Entry and Exit Timing Diagram
.................................................................................. 130
6-17
HALT Wake-Up Using GPIOn
................................................................................................. 132
6-18
PWM Hi-Z Characteristics
..................................................................................................... 133
6-19
ADCSOCAO or ADCSOCBO Timing
........................................................................................ 135
6-20
External Interrupt Timing
....................................................................................................... 135
6-21
SPI Master Mode External Timing (Clock Phase = 0)
..................................................................... 138
6-22
SPI Master Mode External Timing (Clock Phase = 1)
..................................................................... 140
6-23
SPI Slave Mode External Timing (Clock Phase = 0)
....................................................................... 142
6-24
SPI Slave Mode External Timing (Clock Phase = 1)
....................................................................... 143
6-25
Relationship Between XTIMCLK and SYSCLKOUT
....................................................................... 146
6-26
Example Read Access
......................................................................................................... 148
6-27
Example Write Access
......................................................................................................... 149
6-28
Example Read With Synchronous XREADY Access
...................................................................... 151
6-29
Example Read With Asynchronous XREADY Access
..................................................................... 152
6-30
Write With Synchronous XREADY Access
.................................................................................. 154
6-31
Write With Asynchronous XREADY Access
................................................................................ 155
6-32
External Interface Hold Waveform
............................................................................................ 157
6-33
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
.................................................. 158
6-34
ADC Power-Up Control Bit Timing
........................................................................................... 160
6-35
ADC Analog Input Impedance Model
........................................................................................ 161
6-36
Sequential Sampling Mode (Single-Channel) Timing
...................................................................... 162
6-37
Simultaneous Sampling Mode Timing
....................................................................................... 163
6-38
McBSP Receive Timing
........................................................................................................ 167
6-39
McBSP Transmit Timing
....................................................................................................... 167
6-40
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
................................................... 168
6-41
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
................................................... 169
6-42
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
................................................... 170
6-43
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
................................................... 171
6
List of Figures
Copyright © 2010–2014, Texas Instruments Incorporated


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