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SM320C26B Scheda tecnica(PDF) 6 Page - Texas Instruments |
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SM320C26B Scheda tecnica(HTML) 6 Page - Texas Instruments |
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6 / 42 page  SM320C26B SGUS069A – NOVEMBER 2012 – REVISED NOVEMBER 2012 www.ti.com 3.1 Architectural Overview The SM320C26B architecture is based on the SMJ320C25 with a different internal RAM and ROM configuration. The SM320C26B integrates 256 words of on-chip ROM and 1568 words of on-chip RAM compared to 4K words of on-chip ROM and 544 words of on-chip RAM for the SMJ320C25. The SM320C26B is pin for pin compatible with the SMJ320C25. Increased throughput on the SM320C26B for many DSP applications is accomplished by means of single cycle multiply/accumulate instructions with a data move option, eight auxiliary registers with a dedicated arithmetic unit, and faster I/O necessary for data intensive signal processing. The architectural design of the SM320C26B emphasizes overall speed, communication, and flexibility in the processor configuration. Control signals and instructions provide floating point support, block memory transfers, communication to slower off-chip devices, and multiprocessing implementations. Three large on-chip RAM blocks, configurable either as separate program and data spaces or as three contiguous data blocks, provide increased flexibility in system design. Programs of up to 256 words can be masked into the internal program ROM. The remainder of the 64K-word program memory space is located externally. Large programs can execute at full speed from this memory space. Programs can also be downloaded from slow external memory to high speed on-chip RAM. A data memory address space of 64K words is included to facilitate implementation of DSP algorithms. The VLSI implementation of the SM320C26B incorporates all of these features as well as many others, including a hardware timer, serial port, and block data transfer capabilities. 3.2 32-Bit ALU and Accumulator The SM320C26B 32-bit arithmetic logic unit (ALU) and accumulator perform a wide range of arithmetic and logical instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch instructions dependent on the status of the ALU or a single bit in a word. These instruction provide the following capabilities: • Branch to an address specified by the accumulator • Normalize fixed-point numbers contained in the accumulator • Test a specified bit of a word in data memory. One input to the ALU is always provided from the accumulator, and the other input can be provided from the product register (PA) of the multiplier or the input scaling shifter which has fetched data from the RAM on the data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the accumulator. The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The contents of the accumulator remain unchanged. 6 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SM320C26B |
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