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FDC1004QDGSTQ1 Scheda tecnica(PDF) 11 Page - Texas Instruments |
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FDC1004QDGSTQ1 Scheda tecnica(HTML) 11 Page - Texas Instruments |
11 / 29 page S1 S2 S3 S4 Capacitance to Digital Converter I 2C FDC1004Q SDA SCL VDD GND Offset and Gain Calibration Configuration and Data Registers CAPDAC M U X Excitation M U X CIN1 CIN2 CIN3 CIN4 SHLD2 SHLD1 CHA CHB S1 S2 S3 S4 Capacitance to Digital Converter I 2C FDC1004Q SDA SCL VDD GND Offset and Gain Calibration Configuration and Data Registers CAPDAC M U X Excitation M U X CIN1 CIN2 CIN3 CIN4 SHLD2 SHLD1 CHA CHB FDC1004Q www.ti.com SNOSCZ4 – APRIL 2015 Device Functional Modes (continued) Figure 10. Single-Ended Configuration with CAPDAC Disabled Figure 11. Single-Ended Configuration with CAPDAC Enabled 8.4.2 Differential Measurement When the FDC1004Q is used for interfacing to a differential capacitive sensor, each of the two input capacitances must be less than 115 pF. In this configuration the CAPDAC is disabled. The absolute value of the difference between the two input capacitances should be kept below 15 pF to avoid introducing errors in the measurement. In differential measurements, SHLD1 is assigned to CHn and SHLD2 is assigned to CHm, where n < m. For instance in the measurement CIN1 – CIN2, where CHA = CIN1 and CHB = CIN2 (see Table 4), Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: FDC1004Q |
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