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FDC1004QDGSTQ1 Scheda tecnica(PDF) 3 Page - Texas Instruments |
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FDC1004QDGSTQ1 Scheda tecnica(HTML) 3 Page - Texas Instruments |
3 / 29 page 1 2 3 4 5 10 9 8 7 6 SHLD1 CIN1 CIN2 CIN3 CIN4 SDA SCL VDD GND SHLD2 FDC1004Q www.ti.com SNOSCZ4 – APRIL 2015 6 Pin Configuration and Functions DGS Package 10 Pin VSSOP Top View Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. SHLD1 1 A Capacitive Input Active AC Shielding. Capacitive Input. The measured capacitance is connected between the CIN1 pin and GND. If CIN1 2 A not used, this pin should be left as an open circuit. Capacitive Input. The measured capacitance is connected between the CIN2 pin and GND. If CIN2 3 A not used, this pin should be left as an open circuit. Capacitive Input. The measured capacitance is connected between the CIN3 pin and GND. If CIN3 4 A not used, this pin should be left as an open circuit. Capacitive Input. The measured capacitance is connected between the CIN4 pin and GND. If CIN4 5 A not used, this pin should be left as an open circuit. SHLD2 6 A Capacitive Input Active AC Shielding. GND 7 G Ground Power Supply Voltage. This pin should be decoupled to GND, using a low impedance VDD 8 P capacitor, for example in combination with a 1- μF tantalum and a 0.1-μF multilayer ceramic. Serial Interface Clock Input. Connects to the master clock line. Requires pull-up resistor if not SCL 9 I already provided elsewhere in the system. Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up SDA 10 I/O resistor if not provided elsewhere in the system. (1) P=Power, G=Ground, I=Input, O=Output, A=Analog, I/O=Bi-Directional Input/Output Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: FDC1004Q |
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