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AD7475BR Scheda tecnica(PDF) 5 Page - Analog Devices |
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AD7475BR Scheda tecnica(HTML) 5 Page - Analog Devices |
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5 / 16 page  REV. A AD7475/AD7495 –5– SCLK 1 5 13 15 SDATA FOUR LEADING ZEROS THREE-STATE t4 2 34 16 t5 t3 tQUIET tCONVERT t2 THREE-STATE DB11 DB10 DB2 DB0 t6 t7 t8 14 0 0 0 0 B DB1 CS Figure 1. Serial Interface Timing Diagram Timing Example 1 Having fSCLK = 20 MHz and a throughput of 1 MSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 1 µs. With t2 = 10 ns min, this leaves tACQ to be 365 ns. This 365 ns satisfies the requirement of 300 ns for tACQ. From Figure 2, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 45 ns. This allows a value of 195 ns for tQUIET, satisfying the minimum requirement of 100 ns. Timing Example 2 Having fSCLK = 5 MHz and a throughput of 315 KSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 3.174 s. With t2 = 10 ns min, this leaves tacq to be 664 ns. This 664 ns satisfies the requirement of 300 ns for tACQ. From Figure 2, tACQ is comprised of 2.5(1/fSCLK) + t8 + tQUIET, t8 = 45 ns. This allows a value of 119 ns for tQUIET satisfying the minimum requirement of 100 ns. As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 100 ns minimum tQUIET between conversions. In Example 2 the signal should be fully acquired at approximately Point C in Figure 2. SCLK 1 5 13 15 2 34 16 t5 tQUIET tCONVERT t2 t6 t8 14 B CS 45ns tACQUISITION 12.5 (1/fSCLK) 10ns 1/THROUGHPUT C Figure 2. Serial Interface Timing Example 200 A IOL 200 A IOH CL 50pF TO OUTPUT PIN 1.6V Figure 3. Load Circuit for Digital Output Timing Specifications |
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