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CDCVF2510APWR Scheda tecnica(PDF) 1 Page - Texas Instruments |
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CDCVF2510APWR Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 18 page 1 FEATURES APPLICATIONS CLK AVCC VCC 1Y9 1Y8 GND GND 1Y7 1Y6 1Y5 VCC FBIN 1 2 3 4 5 6 7 8 9 10 11 12 AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VCC G FBOUT 24 23 22 21 20 19 18 17 16 15 14 13 PW PACKAGE (TOP VIEW) DESCRIPTION CDCVF2510A www.ti.com ............................................................................................................................................... SCAS764C – MARCH 2004 – REVISED FEBRUARY 2009 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE • DRAM Applications • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification • PLL Based Clock Distributors Rev. 1.1 • Non-PLL Clock Buffer • Spread Spectrum Clock Compatible • Operating Frequency 20 MHz to 175 MHz • Static Phase Error Distribution at 66 MHz to 166 MHz is ±125 ps • Jitter (cyc–cyc) at 66 MHz to 166 MHz is |70| ps • Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption vs Current Generation PC133 Devices • Auto Frequency Detection to Disable Device (Power-Down Mode) • Available in Plastic 24-Pin TSSOP • Distributes One Clock Input to One Bank of 10 Outputs • External Feedback (FBIN) Terminal is Used to Synchronize the Outputs to the Clock Input • 25-Ω On-Chip Series Damping Resistors • No External RC Network Required • Operates at 3.3 V The CDCVF2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The CDCVF2510A uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510A operates at a 3.3-V VCC and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. The device automically goes into power-down mode when no input signal (< 1 MHz) is applied to CLK; the outputs go into a low state. Unlike many products containing PLLs, the CDCVF2510A does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDCVF2510A requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals. The PLL can be bypassed by strapping AVCC to ground to use as a simple clock buffer. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2004–2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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