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CDCLVP110 Scheda tecnica(PDF) 2 Page - Texas Instruments |
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CDCLVP110 Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 14 page CLK_SEL VBB 30 31 29 28 27 26 23 22 24 21 20 19 18 17 15 14 13 12 11 10 5 CLK0 CLK0 CLK1 CLK1 0 1 3 4 6 7 2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q0 Q1 Q2 Q3 Q4 Q5 Q7 Q6 Q9 Q8 CDCLVP110 SCAS683D – JUNE 2002 – REVISED JANUARY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME NO. CLK_SEL 2 Clock select. Used to select between CLK0 and CLK1 input pairs. CLK0, CLK0 3, 4 Differential LVECL/LVPECL input pair CLK1, CLK1 6, 7 Differential HSTL input pair 11, 13, 15, 18, Q [9:0] 20, 22, 24, 27, LVECL/LVPECL clock outputs, these outputs provide low-skew copies of CLKn. 29, 31 10, 12, 14, 17, Q[9:0] 19, 21,23, 26, LVECL/LVPECL complementary clock outputs, these outputs provide copies of CLKn. 28, 30 VBB 5 Reference voltage output for single-ended input operation VCC 1, 9, 16, 25, 32 Supply voltage VEE 8 Device ground or negative supply voltage in ECL mode 2 Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated Product Folder Link(s) :CDCLVP110 |
Codice articolo simile - CDCLVP110_14 |
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Descrizione simile - CDCLVP110_14 |
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