AD7274BRM datasheet(1/20 Pages) AD

Il numero della parte	AD7274BRM

Spiegazioni elettronici	3MSPS,10-/12-Bit ADCs in 8-Lead TSOT

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REV. PrB (

6/04)

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Tel: 781/329-4700

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Fax: 781/326-8703

Analog Devices, Inc., 200

4

3MSPS,10-/12-Bit

ADCs in 8-Lead TSOT

Preliminary Technical Data

AD7273/AD7274

PRELIMINARYTECHNICALDATA

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Fast Throughput Rate: 3MSPS

Specified for VDD of 2.35 V to 3.6V

Low Power:

13.5 mW max at 3MSPS with 3V Supplies

Wide Input Bandwidth:

70dB SNR at 1MHz Input Frequency

Flexible Power/Serial Clock Speed Management

No Pipeline Delays

High Speed Serial Interface

SPITM/QSPITM/MICROWIRETM/DSP Compatible

Power Down Mode: 1µA max

8-Lead TSOT Package

8-Lead MSOP Package

APPLICATIONS

Battery-Powered Systems

Personal Digital Assistants

Medical Instruments

Mobile Communications

Instrumentation and Control Systems

Data Acquisition Systems

High-Speed Modems

Optical Sensors

PRODUCT HIGHLIGHTS

1. 3MSPS ADCs in an 8-lead TSOT package.

2. High Throughput with Low Power Consumption.

3. Flexible Power/Serial Clock Speed Management.

The conversion rate is determined by the serial clock

allowing the conversion time to be reduced through the

serial clock speed increase. This allows the average

power consumption to be reduced when a power-down

mode is used while not converting. The AD7273/

AD7274 features a power down mode to maximize

power efficiency at lower throughput rates. Current con-

sumption is 1

µA max when in Power Down mode.

4. Reference can be driven up to the power supply.

5. No Pipeline Delay.

The parts feature a standard successive-approximation

ADC with accurate control of the sampling instant via a

CS input and once-off conversion control.

GENERAL DESCRIPTION

The AD7273/AD7274 are 10-bit and 12-bit, high speed,

low power, successive-approximation ADCs respectively.

The parts operate from a single 2.35V to 3.6 V power

supply and feature throughput rates up to 3 MSPS. The

parts contain a low-noise, wide bandwidth track/hold am-

plifier which can handle input frequencies in excess of

TBD MHz.

The conversion process and data acquisition are controlled

using

CS and the serial clock, allowing the devices to

interface with microprocessors or DSPs. The input signal

is sampled on the falling edge of

CS and the conversion is

also initiated at this point. The conversion rate is deter-

mined by the SCLK. There are no pipeline delays associ-

ated with the part.

The AD7273/AD7274 use advanced design techniques to

achieve very low power dissipation at high throughput

rates.

The reference for the parts is applied externally and can

be in the range of 1.2V to VDD. This allows the widest

dynamic input range to the ADC.

T/H

SCLK

SDATA

&6

GND

10-/12-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

V

DD

V

IN

AD7273/AD7274

V

REF

GND

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