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CDCFR83 Scheda tecnica(PDF) 10 Page - Texas Instruments |
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CDCFR83 Scheda tecnica(HTML) 10 Page - Texas Instruments |
10 / 15 page CDCFR83 DIRECT RAMBUS CLOCK GENERATOR SCAS665B − APRIL 2001 REVISED OCTOBER 2005 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION PWRDNB CLK/CLKB t(power down) t(power up) Figure 8. PWRDNB Transition Timings MULT0 and/or MULT1 CLK/CLKB t(MULT) Figure 9. MULT Transition Timings STOPB t(CLKOFF) (see Note A) t(ON) t(STOP) t(CLKSETL) t(CLKON) (see Note A) Clock output settled within 50 ps of the phase before disabled Clock enabled and glitch free Output clock not specified glitches ok CLK/CLKB NOTE A: Vref = VO ± 200 mV Figure 10. STOPB Transition Timings |
Codice articolo simile - CDCFR83_08 |
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Descrizione simile - CDCFR83_08 |
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