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CDC2586PAHG4 Scheda tecnica(PDF) 3 Page - Texas Instruments

Il numero della parte CDC2586PAHG4
Spiegazioni elettronici  3.3-V PHASE-LOCK LOOP CLOCK DRIVER
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CDC2586PAHG4 Scheda tecnica(HTML) 3 Page - Texas Instruments

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Output Configuration A
Output Configuration B
CDC2586
SCAS337D – FEBRUARY 1993 – REVISED APRIL 2004
Output configuration A is valid when any output configured as a 1x frequency output in Table 1 is fed back to
FBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputs
configured as 1/2 outputs operate at half the CLKIN frequency, while outputs configured as 1x outputs operate at
the same frequency as CLKIN.
Table 1. Output Configuration A(1)
INPUTS
OUTPUTS
1/2
×
1
×
SEL1
SEL0
FREQUENCY
FREQUENCY
L
L
None
All
L
H
1Yn
2Yn, 3Yn, 4Yn
H
L
1Yn, 2Yn
3Yn, 4Yn
H
H
1Yn, 2Yn, 3Yn
4Yn
(1)
n = 1, 2, 3
Output configuration B is valid when any output configured as a 1x frequency output in Table 2 is fed back to
FBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputs
configured as 1x outputs operate at the CLKIN frequency, while outputs configured as 2x outputs operate at
double the frequency of CLKIN.
Table 2. Output Configuration B(1)
INPUTS
OUTPUTS
1
×
2
×
SEL1
SEL0
FREQUENCY
FREQUENCY
L
L
All
None
L
H
1Yn
2Yn, 3Yn, 4Yn
H
L
1Yn, 2Yn
3Yn, 4Yn
H
H
1Yn, 2Yn, 3Yn
4Yn
(1)
n = 1, 2, 3
3


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