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DAC9881SBRGET Scheda tecnica(PDF) 11 Page - Texas Instruments |
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DAC9881SBRGET Scheda tecnica(HTML) 11 Page - Texas Instruments |
11 / 39 page CS Case1: DaisyChain, tiedlow. LDAC Case2: DaisyChain, active. LDAC SCLK SDI SDO LDAC t 9 t 8 t 4 t 5 t 6 t 3 t 1 t 2 t 7 InputRegister andDACLatch Updated High-Z Low High-Z Bit23(N) (1) Bit0(N) Bit23(N) Bit22(N) Bit23(N+1) Bit0(N+1) Bit0(N) t 11 t 13 t 12 t 10 =Don’tCare Bit23=MSB Bit0=LSB CS SCLK SDI SDO LDAC t 9 t 8 t 4 t 5 t 6 t 3 t 1 t 2 t 7 High-Z High-Z Bit23(N) (1) Bit0(N) Bit23(N) Bit22(N) Bit23(N+1) Bit0(N+1) Bit0(N) t 11 t 13 t 12 t 10 InputRegister Updated High DACLatch Updated t 14 t 15 NOTE:(1)SDOdatadelayedfromSDIby24clockcycles. DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 Figure 3. Timing Diagram for Daisy Chain Mode, Two Cascaded Devices Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): DAC9881 |
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