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74LVCH16901DGGRG4 Scheda tecnica(PDF) 9 Page - Texas Instruments |
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74LVCH16901DGGRG4 Scheda tecnica(HTML) 9 Page - Texas Instruments |
9 / 13 page www.ti.com PARAMETER MEASUREMENT INFORMATION VM From Output Under Test CL (see Note A) LOAD CIRCUIT S1 VLOAD Open GND RL RL Data Input Timing Input VI 0 V VI 0 V 0 V tw Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS PULSE DURATION tPLH tPHL tPHL tPLH VOH VOH VOL VOL VI 0 V Input Output Waveform 1 S1 at VLOAD (see Note B) Output Waveform 2 S1 at GND (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ VLOAD/2 0 V VOL + V∆ VOH − V∆ ≈0 V VI VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Output Output tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Output Control VM VM VM VM VM VM VM VM VM VM VM VM VI VM VM 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V 1 k Ω 500 Ω 500 Ω 500 Ω VCC RL 2 × VCC 2 × VCC 6 V 6 V VLOAD CL 30 pF 30 pF 50 pF 50 pF 0.15 V 0.15 V 0.3 V 0.3 V V∆ VCC VCC 2.7 V 2.7 V VI VCC/2 VCC/2 1.5 V 1.5 V VM tr/tf ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns INPUTS tsu th SN74LVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES145C – OCTOBER 1998 – REVISED JUNE 2005 Figure 1. Load Circuit and Voltage Waveforms 9 Not Recommended For New Designs |
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