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AM5K2E04XABDA4 Scheda tecnica(PDF) 9 Page - Texas Instruments

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Il numero della parte AM5K2E04XABDA4
Spiegazioni elettronici  AM5K2E0x Multicore ARM KeyStone II System-on-Chip (SoC)
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AM5K2E04, AM5K2E02
www.ti.com
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
3.1
ARM CorePac
The ARM CorePac of the AM5K2E0x integrates a Cortex-A15 Cluster (4 Cortex-A15 processors) with
additional logic for bus protocol conversion, emulation, interrupt handling, and debug related
enhancements. The Cortex-A15 processor is an ARMv7A-compatible, multi-issue out-of-order, superscalar
pipeline with integrated L1 caches. The implementation also supports advanced SIMDV2 (Neon
technology) and VFPv4 (Vector Floating Point) architecture extensions, security, virtualization, LPAE
(Large Physical Address Extension), and multiprocessing extensions. The quad core cluster includes a
4MB L2 cache and support for AMBA4 AXI and AXI Coherence Extension (ACE) protocols. For more
information see the KeyStone II Architecture ARM CorePac User's Guide User Guide (SPRUHJ4).
Copyright © 2012–2015, Texas Instruments Incorporated
Device Characteristics
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