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SN74ALVCH162836DGGR Scheda tecnica(PDF) 1 Page - Texas Instruments

Il numero della parte SN74ALVCH162836DGGR
Spiegazioni elettronici  20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

SN74ALVCH162836DGGR Scheda tecnica(HTML) 1 Page - Texas Instruments

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FEATURES
DESCRIPTION
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
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28
56
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36
35
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31
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29
OE
Y1
Y2
GND
Y3
Y4
VCC
Y5
Y6
Y7
GND
Y8
Y9
Y10
Y11
Y12
Y13
GND
Y14
Y15
Y16
VCC
Y17
Y18
GND
Y19
Y20
NC
CLK
A1
A2
GND
A3
A4
VCC
A5
A6
A7
GND
A8
A9
A10
A11
A12
A13
GND
A14
A15
A16
VCC
A17
A18
GND
A19
A20
LE
NC − No internal connection
The output port includes equivalent 26-
Ω series resistors to reduce overshoot and undershoot.
SN74ALVCH162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES122F – JULY 1997 – REVISED OCTOBER 2004
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Output Port Has Equivalent 26-
Ω Series
Resistors, So No External Resistors Are
Required
Designed to Comply With JEDEC 168-Pin and
200-Pin SDRAM Buffered DIMM Specification
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink Small-Outline
(DGG), and Thin Very Small-Outline (DGV)
Packages
NOTE: For tape-and-reel order entry, the DGGR package is
abbreviated to GR, and the DGVR package is abbreviated
to VR.
This 20-bit universal bus driver is designed for 1.65-V
to 3.6-V VCC operation.
Data
flow
from
A
to
Y
is
controlled
by
the
output-enable (OE) input. The device operates in the
transparent mode when the latch-enable (LE) input is
low. When LE is high, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If
LE is high, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLK. When OE is high,
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162836 is characterized for operation from -40
°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1997–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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