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74ALVCH16646DLRG4 Scheda tecnica(PDF) 1 Page - Texas Instruments

Il numero della parte 74ALVCH16646DLRG4
Spiegazioni elettronici  16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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74ALVCH16646DLRG4 Scheda tecnica(HTML) 1 Page - Texas Instruments

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FEATURES
DESCRIPTION
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
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1DIR
1CLKAB
1SAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
1OE
1CLKBA
1SBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OE
SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES032F – JULY 1995 – REVISED SEPTEMBER 2004
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
This 16-bit bus transceiver and register is designed
for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16646 can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the A
or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock (CLKAB
or CLKBA) input. Figure 1 illustrates the four
fundamental bus-management functions that can be
performed with the SN74ALVCH16646.
Output-enable (OE) and direction-control (DIR) inputs
are provided to control the transceiver functions. In
the
transceiver
mode,
data
present
at
the
high-impedance port may be stored in either register
or in both. The select-control (SAB and SBA) inputs
can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the
typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR
determines which bus receives data when OE is low. In the isolation mode (OE high), A data may be stored in
one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16646 is characterized for operation from -40
°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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