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74ACT11074DBLE Scheda tecnica(PDF) 1 Page - Texas Instruments

Il numero della parte 74ACT11074DBLE
Spiegazioni elettronici  DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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74ACT11074DBLE Scheda tecnica(HTML) 1 Page - Texas Instruments

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74ACT11074
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS498A – DECEMBER 1986 – REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Inputs Are TTL-Voltage Compatible
D Center-Pin VCC and GND Configurations to
Minimize High-Speed Switching Noise
D EPICt (Enhanced-Performance Implanted
CMOS) 1-
mm Process
D 500-mA Typical Latch-Up Immunity
at 125
°C
D Package Options Include Plastic
Small-Outline (D) and Shrink Small-Outline
(DB) Packages, and Standard Plastic
300-mil DIPs (N)
description
This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)
or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR
are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs
on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed
without affecting the levels at the outputs.
The 74ACT11074 is characterized for operation from –40
°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
LX
XL
H
L
LX
X
H{
H{
H
H
HH
L
H
H
LL
H
H
H
L
X
Q0
Q0
† This configuration is unstable; that is, it does not
persist when either PRE or CLR returns to its
inactive (high) level.
Copyright
© 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1PRE
1Q
1Q
GND
2Q
2Q
2PRE
1CLK
1D
1CLR
VCC
2CLR
2D
2CLK
D, DB, OR N PACKAGE
(TOP VIEW)


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