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74AC11651DW Scheda tecnica(PDF) 8 Page - Texas Instruments |
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74AC11651DW Scheda tecnica(HTML) 8 Page - Texas Instruments |
8 / 10 page 74AC11651 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3STATE OUTPUTS SCAS135 − MARCH 1990 − REVISED APRIL 1993 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION th tsu From Output Under Test CL = 50 pF LOAD CIRCUIT FOR OUTPUTS S1 2 × VCC Open GND 500 Ω 500 Ω TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 × VCC GND Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note C) Output Waveform 2 S1 at GND (see Note C) VOL VOH tPZL tPZH tPLZ tPHZ 50% 50% ≈ VCC 0 V 50% VCC 0 V VCC Data Input Timing Input 50% VCC 0 V 50% 50% 0 V VCC 0 V 50% 50% tw Input (see Note A) 50% VCC 20% VCC 80% VCC tPLH tPHL 50% 50% 0 V 50% VCC 50% VCC VOH VOL Input (see Note B) Output (see Note D) VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VCC VCC NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms |
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