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74AC11898DW Scheda tecnica(PDF) 4 Page - Texas Instruments |
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74AC11898DW Scheda tecnica(HTML) 4 Page - Texas Instruments |
4 / 7 page 74AC11898 10BIT PARALLELOUT SERIAL SHIFT REGISTER SCAS143 − OCTOBER 1990 − REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 2−4 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25 °C MIN MAX UNIT PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX UNIT 3 V 2.9 2.9 IOH = − 50 µA 4.5 V 4.4 4.4 IOH = − 50 µA 5.5 V 5.4 5.4 VOH IOH = − 4 mA 3 V 2.58 2.48 V VOH IOL = − 24 mA 4.5 V 3.94 3.8 V IOL = − 24 mA 5.5 V 4.94 4.8 IOH = − 75 mA† 5.5 V 3.85 3 V 0.1 0.1 IOL = 50 µA 4.5 V 0.1 0.1 IOL = 50 µA 5.5 V 0.1 0.1 VOL IOL = 12 mA 3 V 0.36 0.44 V VOL IOL = 24 mA 4.5 V 0.36 0.44 V IOL = 24 mA 5.5 V 0.36 0.44 IOL = 75 mA† 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 µA ICC VI = VCC or GND, IO = 0 5.5 V 8 80 µA Ci VI = VCC or GND 5 V 4 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER TA = 25°C MIN MAX UNIT PARAMETER MIN MAX MIN MAX UNIT fclock Clock frequency 0 40 0 40 ns tw Pulse duration CLR low 5 5 ns tw Pulse duration CLK high or low 12.5 12.5 ns tsu Setup time before CLK ↑ Data 14 14 ns tsu Setup time before CLK ↑ CLR inactive 1.5 1.5 ns th Hold time, data after CLK ↑ 0 0 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER TA = 25°C MIN MAX UNIT PARAMETER MIN MAX MIN MAX UNIT fclock Clock frequency 0 60 0 60 ns tw Pulse duration CLR low 4.5 4.5 ns tw Pulse duration CLK high or low 8.3 8.3 ns tsu Setup time before CLK ↑ Data 8.5 8.5 ns tsu Setup time before CLK ↑ CLR inactive 1.5 1.5 ns th Hold time, data after CLK ↑ 0 0 ns |
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