74AC11379

QUAD D-TYPE FLIP-FLOP

WITH CLOCK ENABLE

SCAS104 − MARCH 1990 − REVISED APRIL 1993

Copyright

1

POST OFFICE BOX 655303

Outputs

Clocking

Registers, Shift Registers, Pattern

Generators

Layout

Configurations Minimize High-Speed

Switching Noise

CMOS) 1-

µm Process

125

°C

Small-Outline Packages and Standard

Plastic 300-mil DIPs

description

These circuits are positive-edge-triggered D-type flip-flops with a clock-enable input.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the

positive-going edge of the clock pulse if the clock-enable input (CLKEN) is low. Clock triggering occurs at a

particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock

input is at either the high or low level, the data (D) input signal has no effect at the output. The circuits are

designed to prevent false clocking by transitions at the clock-enable (CLKEN) input.

The 74AC11379 is characterized for operation from − 40

°C to 85°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

CLKEN

CLK

D

Q

Q

H

X

X

Q0

Q0

L

↑

HH

L

L

↑

LL

H

X

L

X

Q0

Q0

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC is a trademark of Texas Instruments Incorporated.

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

1Q

2Q

2Q

GND

GND

GND

GND

3Q

3Q

4Q

1Q

CLKEN

1D

2D

3D

4D

CLK

4Q

DW OR N PACKAGE

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