ADC08D1000QML-SP datasheet(5/50 Pages) TI1

Il numero della parte	ADC08D1000QML-SP

Spiegazioni elettronici	High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter

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Produttore elettronici	TI1 [Texas Instruments]

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VA

GND

V

A

200k

8 pF

V

CMO

Enable AC

Coupling

50k

VA

AGND

VA

AGND

50k

Control from VCMO

VCMO

100

VA

AGND

18

VA

AGND

19

100

VBIAS

50k

ADC08D1000QML, ADC08D1000QML-SP

ADC08D1000WG-QV

www.ti.com

SNAS352G – JANUARY 2007 – REVISED MARCH 2013

Pin Descriptions and Equivalent Circuits (continued)

Pin Functions

Pin No.

Symbol

Equivalent Circuit

Description

LVDS Clock input pins for the ADC. The differential clock signal

must be a.c. coupled to these pins. The input signal is sampled on

18

CLK+

the falling edge of CLK+. See Acquiring the Input for a description

19

CLK-

of acquiring the input and THE CLOCK INPUTS for an overview of

the clock inputs.

11

VINI+

10

VINI−

Analog signal inputs to the ADC. The differential full-scale input

.

range is 650 mVP-P when the FSR pin is low, or 870 mVP-P when

22

VINQ+

the FSR pin is high.

23

VINQ−

Common Mode Voltage. The voltage output at this pin is required

to be the common mode input voltage at VIN+ and VIN− when d.c.

7

VCMO

coupling is used. This pin should be grounded when a.c. coupling

is used at the analog inputs. This pin is capable of sourcing or

sinking 100

μA. See THE ANALOG INPUT.

31

VBG

Bandgap output voltage capable of 100

μA source/sink.

Calibration Running indication. This pin is at a logic high when

126

CalRun

calibration is running.

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