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ADC10065 Scheda tecnica(PDF) 6 Page - Texas Instruments |
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ADC10065 Scheda tecnica(HTML) 6 Page - Texas Instruments |
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6 / 26 page  ADC10065 SNAS225H – JULY 2003 – REVISED APRIL 2013 www.ti.com Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V (External), fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. (1) (2) (3) (4). Parameter Test Conditions Min Typ Max Units STATIC CONVERTER CHARACTERISTICS No Missing Codes ensured 10 Bits FIN = 500 kHz, −0 dB Full INL Integral Non-Linearity −1.0 ±0.3 +1.1 LSB Scale FIN = 500 kHz, −0 dB Full DNL Differential Non-Linearity −0.9 ±0.3 +0.9 LSB Scale Positive Error −1.5 +0.4 +1.9 % FS GE Gain Error Negative Error −1.5 +0.03 +1.9 % FS OE Offset Error (VIN+ = VIN−) −1.4 0.2 +1.7 % FS Under Range Output Code 0 Over Range Output Code 1023 FPBW Full Power Bandwidth (5) 400 MHz REFERENCE AND INPUT CHARACTERISTICS VCM Common Mode Input Voltage 0.5 1.5 V Output Voltage for use as an input VCOM 1.45 V common mode voltage (6) VREF Reference Voltage 1.2 V Reference Voltage Temperature VREFTC ±80 ppm/°C Coefficient VIN Input Capacitance (each pin to CIN 4 pF VSSA) POWER SUPPLY CHARACTERISTICS STBY = 1 4.7 6.0 mA IVDDA Analog Supply Current STBY = 0 22 29 mA STBY = 1, fIN = 0 Hz 0 mA IVDDIO Digital Supply Current (7) STBY 0, fIN = 0 Hz 0.97 1.2 mA STBY = 1 14.1 18.0 mW PWR Power Consumption (8) STBY = 0 68.4 90 mW (1) To ensure accuracy, it is required that |VDDA–VDDIO| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. (2) With the test condition for 2 VP-P differential input, the 10-bit LSB is 1.95 mV. (3) Typical figures are at TA = TJ = 25°C and represent most likely parametric norms. Test limits are specified to Texas Instrument's AOQL (Average Outgoing Quality Level). (4) The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage this device. However, input errors will be generated if the input goes above VDDA or VDDIO and below VSSA or VSSIO. See Figure 2 (5) The input bandwidth is limited using a capacitor between VIN − and V IN +. (6) VCOM is a typical value, measured at room temperature. It is not specified by test. Do not load this pin. (7) IDDIO is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR = VDR x (C0 x f0 + C1 x f1 + C2 + f2 +....C11 x f11) where VDR is the output driver supply voltage, Cn is the total load capacitance on the output pin, and fn is the average frequency at which the pin is toggling. (8) Power consumption includes output driver power. (fIN = 0 MHz). 6 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: ADC10065 |
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