ADC10D1000 datasheet(5/82 Pages) TI1

Il numero della parte	ADC10D1000

Spiegazioni elettronici	Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC

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Produttore elettronici	TI1 [Texas Instruments]

Homepage	http://www.ti.com

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5 / 82 page

VA

AGND

VA

AGND

100

VA

AGND

VA

AGND

100

VBIAS

50k

VA

AGND

VA

AGND

50k

Control from VCMO

VCMO

100

ADC10D1000, ADC10D1500

www.ti.com

SNAS462Q – OCTOBER 2008 – REVISED MARCH 2013

Ball Descriptions and Equivalent Circuits

Table 3. Analog Front-End and Clock Balls

Ball No.

Name

Equivalent Circuit

Description

Differential signal I- and Q-inputs. In the Non-Dual

Edge Sampling (Non-DES) Mode, each I- and Q-

input is sampled and converted by its respective

channel with each positive transition of the CLK

input. In Non-ECM (Non-Extended Control Mode)

and DES Mode, both channels sample the I-input.

In Extended Control Mode (ECM), the Q-input

may optionally be selected for conversion in DES

Mode by the DEQ Bit (Addr: 0h, Bit 6).

Each I- and Q-channel input has an internal

common mode bias that is disabled when DC-

H1/J1

VinI+/-

coupled Mode is selected. Both inputs must be

N1/M1

VinQ+/-

either AC- or DC-coupled. The coupling mode is

selected by the VCMO Pin.

In Non-ECM, the full-scale range of these inputs is

determined by the FSR Pin; both I- and Q-

channels have the same full-scale input range. In

ECM, the full-scale input range of the I- and Q-

channel inputs may be independently set via the

Control Register (Addr: 3h and Addr: Bh). Note

that the high and low full-scale input range setting

in Non-ECM corresponds to the mid and minimum

full-scale input range in ECM.

The input offset may also be adjusted in ECM.

Differential Converter Sampling Clock. In the Non-

DES Mode, the analog inputs are sampled on the

positive transitions of this clock signal. In the DES

U2/V1

CLK+/-

Mode, the selected input is sampled on both

transitions of this clock. This clock must be AC-

coupled.

Differential DCLK Reset. A positive pulse on this

input is used to reset the DCLKI and DCLKQ

outputs of two or more ADC10D1000/1500s in

order to synchronize them with other

ADC10D1000/1500s in the system. DCLKI and

DCLKQ are always in phase with each other,

V2/W1

DCLK_RST+/-

unless one channel is powered down, and do not

require a pulse from DCLK_RST to become

synchronized. The pulse applied here must meet

timing relationships with respect to the CLK input.

Although supported, this feature has been

superseded by AutoSync.

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