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74AC11138DR Scheda tecnica(PDF) 1 Page - Texas Instruments

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Il numero della parte 74AC11138DR
Spiegazioni elettronici  3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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74AC11138DR Scheda tecnica(HTML) 1 Page - Texas Instruments

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74AC11138
3LINE TO 8LINE DECODER/DEMULTIPLEXER
SCAS042B − MAY 1988 − REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
D Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
D Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
D Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D EPIC (Enhanced-Performance Implanted
CMOS) 1-
µm Process
D 500-mA Typical Latch-Up Immunity at
125
°C
D Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
description
The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing
applications requiring very short propagation delay times. In high-performance memory systems, this decoder
can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing
a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than
the typical access time of the memory. This means that the effective system delay introduced by the decoder
is negligible.
The conditions at the binary-select (A, B, C) inputs and the three enable (G1, G2A, G2B) inputs select one of
eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line
decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
The 74AC11138 is characterized for operation from −40
°C to 85°C.
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1
G2A
G2B
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
XH
X
XX
H
HH
HH
HH
H
L
XX
X
XX
H
HH
HH
HH
H
H
LL
L
LL
L
HH
HH
HH
H
H
LL
L
LH
H
L
H
HH
HH
H
H
LL
L
HLH
H
L
HH
HH
H
H
LL
L
HH
H
HH
L
H
HH
H
H
LL
H
LL
H
HH
H
L
HH
H
H
LL
H
LH
H
HH
HH
L
H
H
H
LL
H
HLH
HH
HH
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
Copyright
 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Y1
Y2
Y3
GND
Y4
Y5
Y6
Y7
Y0
A
B
C
VCC
G1
G2A
G2B
D, N, OR PW PACKAGE
(TOP VIEW)


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