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TSC2102IDAR Scheda tecnica(PDF) 9 Page - Texas Instruments |
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TSC2102IDAR Scheda tecnica(HTML) 9 Page - Texas Instruments |
9 / 54 page TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 www.ti.com 9 th(WS) ts(WS) ts (DI) th(DI) LRCK BCLK DIN tL(BCLK) tH(BCLK) tP(BCLK) Figure 3. I2S/LJF/RJF Timing in Slave Mode TYPICAL TIMING REQUIREMENTS All specifications at 25 °C, IOVDD = 3.3 V, DVDD = 1.8 V(1) PARAMETER MIN MAX UNITS tH (BCLK) BCLK high period 35 ns tL (BCLK) BCLK low period 35 ns tP (BCLK) BCLK period 85 ns ts(WS) LRCK setup 6 ns th(WS) LRCK hold 6 ns ts(DI) DIN setup 6 ns th(DI) DIN hold 6 ns tr Rise time 4 ns tf Fall time 4 ns (1) These parameters are based on characterization and are not tested in production. th(WS) ts(WS) ts (DI) th(DI) LRCK BCLK DIN tH(BCLK) tL(BCLK) tP(BCLK) ts(WS) th(WS) Figure 4. DSP Timing in Slave Mode TYPICAL TIMING REQUIREMENTS All specifications at 25 °C, IOVDD = 3.3 V, DVDD = 1.8 V(1) PARAMETER MIN MAX UNITS tH (BCLK) BCLK high period 35 ns tL (BCLK) BCLK low period 35 ns tP (BCLK) BCLK period 85 ns ts(WS) LRCK setup 6 ns th(WS) LRCK hold 6 ns ts(DI) DIN setup 6 ns th(DI) DIN hold 6 ns tr Rise time 4 ns tf Fall time 4 ns (1) These parameters are based on characterization and are not tested in production. |
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