REV. B

AD1981B

–10–

Reset Register (Index 00h)

NOTES

X in the above table is a wild card and has no effect on the value.

Writing any value to this register performs a register reset that causes all registers to revert to their default values (except 74h, which forces the serial configuration).

Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.

ID[9:0] Identify Capability. The ID decodes the capabilities of AD1981B based on the following:

SE[4:0] Stereo Enhancement. The AD1981B does not provide hardware 3D stereo enhancement (all bits are zeros).

Master Volume Register (Index 02h)

* For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved.

Refer to Table I for examples. This register controls the Line_Out volume controls for both stereo channels and the mute bit. Each

volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume

registers, to maintain compatibility whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically

set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1.

RMV[4:0]

Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from

0 dB to a maximum attenuation of 46.5 dB.

RM

Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the MM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1.

LMV[4:0]

Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from

0 dB to a maximum attenuation of 46.5 dB.

MM

Master Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT

bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.

Bit

Function

AD1981B

ID0

Dedicated Mic PCM In Channel

0

ID1

Modem Line Codec Support

0

ID2

Bass and Treble Control

0

ID3

Simulated Stereo (Mono to Stereo)

0

ID4

Headphone Out Support

1

ID5

Loudness (Bass Boost) Support

0

ID6

18-Bit DAC Resolution

0

ID7

20-Bit DAC Resolution

1

ID8

18-Bit ADC Resolution

0

ID9

20-Bit ADC Resolution

0

Reg

No.

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

00h

Reset

X

SE4

SE3

SE2

SE1

SE0

ID9

ID8

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

0090h

Reg

No.

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

02h

Master

MM

X

X

LMV4

LMV3

LMV2

LMV1

LMV0 RM

* XX

RMV4

RMV3 RMV2 RMV1 RMV0 8000h

Volume