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TMP320R2812GHHS Scheda tecnica(PDF) 6 Page - Texas Instruments

Il numero della parte TMP320R2812GHHS
Spiegazioni elettronici  TMS320R2811, TMS320R2812 Digital Signal Processors
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Produttore elettronici  TI [Texas Instruments]
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Figures
6
June 2004
SPRS257
List of Figures
Figure
Page
Figure 2−1. TMS320R2812 179-Ball GHH and ZHH MicroStar BGA (Bottom View)
14
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Figure 2−2. TMS320R2812 176-Pin PGF LQFP (Top View)
15
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Figure 2−3. TMS320R2811 128-Pin PBK LQFP (Top View)
16
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Figure 3−1. Functional Block Diagram
27
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Figure 3−2. R2812 Memory Map
28
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Figure 3−3. R2811 Memory Map
29
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Figure 3−4. External Interface Block Diagram
38
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Figure 3−5. Interrupt Sources
40
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Figure 3−6. Multiplexing of Interrupts Using the PIE Block
41
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Figure 3−7. Clock and Reset Domains
44
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Figure 3−8. OSC and PLL Block
46
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Figure 3−9. Recommended Crystal/Clock Connection
47
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Figure 3−10. Watchdog Module
48
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Figure 4−1. CPU-Timers
50
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Figure 4−2. CPU-Timer Interrupts Signals and Output Signal
51
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Figure 4−3. Event Manager A Functional Block Diagram
55
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Figure 4−4. Block Diagram of the R281x ADC Module
59
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Figure 4−5. ADC Pin Connections With Internal Reference
60
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Figure 4−6. ADC Pin Connections With External Reference
61
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Figure 4−7. eCAN Block Diagram and Interface Circuit
64
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Figure 4−8. eCAN Memory Map
65
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Figure 4−9. McBSP Module With FIFO
68
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Figure 4−10. Serial Communications Interface (SCI) Module Block Diagram
72
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Figure 4−11. Serial Peripheral Interface Module Block Diagram (Slave Mode)
76
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Figure 4−12. Modes of Operation
79
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Figure 5−1. TMS320x28x Device Nomenclature
81
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−1. R2812/R2811 Typical Current Consumption (With Peripheral Clocks Enabled)
87
. . . . . . . . . . . . . . . .
Figure 6−2. Output Levels
88
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Figure 6−3. Input Levels
88
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Figure 6−4. 3.3-V Test Load Circuit
89
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Figure 6−5. Clock Timing
92
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Figure 6−6. Power-on Reset in Microcomputer Mode (XMP/MC = 0)
93
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−7. Power-on Reset in Microprocessor Mode (XMP/MC = 1)
94
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Figure 6−8. Warm Reset in Microcomputer Mode
95
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Figure 6−9. Effect of Writing Into PLLCR Register
96
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Figure 6−10. IDLE Entry and Exit Timing
97
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Figure 6−11. STANDBY Entry and Exit Timing
98
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Figure 6−12. HALT Wakeup Using XNMI
99
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Figure 6−13. PWM Output Timing
100
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Figure 6−14. TDIRx Timing
100
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