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FM25V01A Scheda tecnica(PDF) 9 Page - Cypress Semiconductor |
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FM25V01A Scheda tecnica(HTML) 9 Page - Cypress Semiconductor |
9 / 22 page FM25V01A Document Number: 001-90881 Rev. *E Page 9 of 22 requires an additional dummy byte. After receiving the opcode, address, and a dummy byte, the FM25V01A starts driving its SO line with data bytes, with the MSB first, and continues trans- mitting as long as the device is selected and the clock is available. In case of bulk read, the internal address counter is incremented automatically, and after the last address 3FFFh is reached, the counter rolls over to 0000h. When the device is driving data on its SO line, any transition on its SI line is ignored. The rising edge of CS terminates a fast read operation and tristates the SO pin. A Fast Read operation is shown in Figure 12. Figure 10. Memory Write (WREN not shown) Operation Figure 11. Memory Read Operation Figure 12. Fast Read Operation CS SCK SO 0123 4 5 6 7 0 7 6 5 4 3 2 1 12 13 14 15 01234567 MSB LSB Data D0 D1 D2 D3 D4 D5 D6 D7 SI Opcode 0 0 0 0 001 X X A13 A12 A11 A9 0 A10 A8 A3 A1 A2 A0 14-bit Address MSB LSB HI-Z CS SCK SO 01 23 456 7 0 7 6 5 4 3 2 1 12 13 14 15 0123 45 6 7 MSB LSB Data SI Opcode 00 0 0 0 0 1 X X A13 A12 A11 A9 1 A10 A8 A3 A1 A2 A0 14-bit Address MSB LSB D0 D1 D2 D3 D4 D5 D6 D7 HI-Z CS SCK SO 0123 4 5 6 7 0 7 6 5 4 3 2 1 12131415 16 17 18 19 20 21 22 23 Data SI Opcode 0 0 0 0 101 X X A13 A11 A9 1 A10 A8 A3 A1 A2 A0 14-bit Address MSB LSB MSB LSB D0 D1 D2 D3 D4 D5 D6 D7 0123 45 67 X X X X X X X X Dummy Byte HI-Z A12 |
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