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FM24V02A-G Scheda tecnica(PDF) 7 Page - Cypress Semiconductor |
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FM24V02A-G Scheda tecnica(HTML) 7 Page - Cypress Semiconductor |
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7 / 19 page  FM24V02A Document Number: 001-90839 Rev. *G Page 7 of 19 Data Transfer After the address bytes have been transmitted, data transfer between the bus master and the FM24V02A can begin. For a read operation the FM24V02A will place 8 data bits on the bus then wait for an acknowledge from the master. If the acknowledge occurs, the FM24V02A will transfer the next sequential byte. If the acknowledge is not sent, the FM24V02A will end the read operation. For a write operation, the FM24V02A will accept 8 data bits from the master then sends an acknowledge. All data transfer occurs MSB (most significant bit) first. Memory Operation The FM24V02A is designed to operate in a manner very similar to other two-wire interface memory products. The major differ- ences result from the higher performance write capability of F-RAM technology. These improvements result in some differ- ences between the FM24V02A and a similar configuration EEPROM during writes. The complete operation for both writes and reads is explained below. Write Operation All writes begin with a slave address, then a memory address. The bus master indicates a write operation by setting the LSB of the slave address (R/W bit) to a '0'. After addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. Any number of sequential bytes may be written. If the end of the address range is reached internally, the address counter will wrap from 7FFFh to 0000h. Unlike other nonvolatile memory technologies, there is no effective write delay with F-RAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory cycle occurs in less time than a single bus clock. Therefore, any operation including read or write can occur immediately following a write. Acknowledge polling, a technique used with EEPROMs to determine if a write is complete is unnecessary and will always return a ready condition. Internally, an actual memory write occurs after the 8th data bit is transferred. It will be complete before the acknowledge is sent. Therefore, if the user desires to abort a write without altering the memory contents, this should be done using START or STOP condition prior to the 8th data bit. The FM24V02A uses no page buffering. The memory array can be write-protected using the WP pin. Setting the WP pin to a HIGH condition (VDD) will write-protect all addresses. The FM24V02A will not acknowledge data bytes that are written to protected addresses. In addition, the address counter will not increment if writes are attempted to these addresses. Setting WP to a LOW state (VSS) will disable the write protect. WP is pulled down internally. Figure 8 and Figure 9 illustrate a single-byte and multiple-byte write cycles in Fast-mode Plus (Fm+). Figure 10 illustrates a single-byte write cycles in Hs mode. Figure 8. Single-Byte Write S A Slave Address 0 Address MSB A Data Byte A P By Master By F-RAM Start Address & Data Stop Acknowledge Address LSB A Figure 9. Multi-Byte Write S A Slave Address 0 Address MSB A Data Byte A P By Master By F-RAM Start Address & Data Stop Acknowledge Address LSB A Data Byte A |
Codice articolo simile - FM24V02A-G |
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Descrizione simile - FM24V02A-G |
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