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LM2743MTCX Scheda tecnica(PDF) 9 Page - National Semiconductor (TI) |
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LM2743MTCX Scheda tecnica(HTML) 9 Page - National Semiconductor (TI) |
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9 / 23 page  Block Diagram 20095203 Application Information THEORY OF OPERATION The LM2743 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high efficiency buck convert- ers. It has output shutdown (SD), input undervoltage lock-out (UVLO) mode and power good (PWGD) flag (based on overvoltage and undervoltage detection). The overvoltage and undervoltage signals are OR-gated to drive the power good signal and provide a logic signal to the system if the output voltage goes out of regulation. Current limit is achieved by sensing the voltage V DS across the low side MOSFET. START UP/SOFT-START When V CC exceeds 2.76V and the shutdown pin (SD) sees a logic high, the soft-start period begins. Then an internal, fixed 10 µA source begins charging the soft-start capacitor. During soft-start the voltage on the soft-start capacitor C SS is connected internaly to the non-inverting input of the error amplifier. The soft-start period lasts until the voltage on the soft-start capacitor exceeds the LM2743 reference voltage of 0.6V. At this point the reference voltage takes over at the non-inverting error amplifier input. The capacitance of C SS determines the length of the soft-start period, and can be approximated by: Where C SS is in µF and tSS is in ms. During soft start the Power Good flag is forced low and it is released when the FB pin voltage reaches 70% of 0.6V. At this point the chip enters normal operation mode, and the output overvoltage and undervoltage monitoring starts. NORMAL OPERATION While in normal operation mode, the LM2743 regulates the output voltage by controlling the duty cycle of the high side and low side MOSFETs (see Typical Application Circuit).The equation governing output voltage is: The PWM frequency is adjustable between 50 kHz and 1 MHz and is set by an external resistor, R FADJ, between the FREQ pin and ground. The resistance needed for a desired frequency is approximately: www.national.com 9 |
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