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ADM1278-1ACPZ Scheda tecnica(PDF) 8 Page - Analog Devices |
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ADM1278-1ACPZ Scheda tecnica(HTML) 8 Page - Analog Devices |
8 / 61 page ADM1278 Data Sheet Rev. A | Page 8 of 61 Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments Nominal Bus Voltage VDD 2.7 5.5 V 3 V to 5 V ± 10% Capacitance for SDA, SCL Pins CPIN 5 pF Input Glitch Filter tSP 0 50 ns 1 Dual function pin names are referenced by the relevant function only (see the Pin Configurations and Function Descriptions section for full pin mnemonics and descriptions). 2 Sampled during initial release to ensure compliance, but not subject to production testing. POWER MONITORING ACCURACY SPECIFICATIONS Table 3. AA Grade A Grade B Grade Parameter Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions/Comments CURRENT AND VOLTAGE MONITORING Current Sense Absolute Error VCC = 4.5 V to 15 V; VMO+ = 2 V to 15 V, 128-sample averaging (unless otherwise noted) ±0.25 ±0.7 ±1.0 % VSENSE_MO = 25 mV ±0.04 ±0.3 ±0.04 ±0.7 ±1.0 % VSENSE_MO = 20 mV ±0.5 ±1.0 ±1.5 % VSENSE_MO = 20 mV; 16-sample averaging ±1.5 ±2.8 ±4.0 % VSENSE_MO = 20 mV; one-sample averaging ±0.3 ±0.8 ±1.1 % VSENSE_MO = 15 mV ±0.4 ±1.1 ±1.5 % VSENSE_MO = 10 mV ±0.75 ±2.0 ±3.0 % VSENSE_MO = 5 mV ±1.6 ±4.3 ±6.2 % VSENSE_MO = 2.5 mV HS+/VOUT Absolute Error ±0.35 ±1.0 ±1.5 % VHS+, VOUT = 10 V to 20 V ±0.5 ±1.0 ±1.5 % VHS+, VOUT = 5 V Power Absolute Error ±0.65 ±1.7 ±2.5 % VSENSE_MO = 20 mV, VHS+ = 12 V SERIAL BUS TIMING CHARACTERISTICS Table 4. Parameter Description Min Typ Max Unit fSCLK Clock frequency 400 kHz tBUF Bus free time 1.3 μs tHD;STA Start hold time 0.6 μs tSU;STA Start setup time 0.6 μs tSU;STO Stop setup time 0.6 μs tHD;DAT SDA hold time 300 900 ns tSU;DAT SDA setup time 100 ns tLOW SCL low time 1.3 μs tHIGH SCL high time 0.6 μs tR1 SCL, SDA rise time 20 300 ns tF1 SCL, SDA fall time 20 300 ns 1 tR = (VIL(MAX) − 0.15) to (VIH3V3 + 0.15) and tF = 0.9 VDD to (VIL(MAX) − 0.15); where VIH3V3 = 2.1 V, and VDD = 3.3 V. VIH3V3 is the input high voltage when VDD = 3.3 V. |
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