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AD7768-4BSTZ-RL Scheda tecnica(PDF) 8 Page - Analog Devices |
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AD7768-4BSTZ-RL Scheda tecnica(HTML) 8 Page - Analog Devices |
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8 / 99 page  AD7768/AD7768-4 Data Sheet Rev. A | Page 8 of 99 Parameter Test Conditions/Comments Min Typ Max Unit Sinc5 Filter FILTER = 1 Decimation Rate Up to six selectable decimation rates; see the Decimation Rate Control section 32 1024 Group Delay Latency 3/ODR sec Settling Time Complete settling, see Table 36 7/ODR sec Pass Band −3 dB bandwidth 0.204 × ODR Hz REJECTION AC Power Supply Rejection Ratio (PSRR) VIN = 0.1 V, AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 2.5 V AVDD1 90 dB AVDD2 100 dB IOVDD 75 dB DC PSRR VIN = 1 V AVDD1 100 dB AVDD2 118 dB IOVDD 90 dB Analog Input Common-Mode Rejection Ratio (CMRR) DC VIN = 0.1 V 95 dB AC Up to 10 kHz 95 dB Crosstalk −0.5 dBFS input on adjacent channels −120 dB CLOCK Crystal Frequency 8 32.768 34 MHz External Clock (MCLK) See the Timing Specifications section 32.768 MHz Duty Cycle For data sheet performance 50:50 % MCLK Pulse Width2 Functionality Logic Low 12.2 ns Logic High 12.2 ns CMOS Clock Input Voltage See the logic inputs parameter High, VINH Low, VINL LVDS Clock2 RL = 100 Ω Differential Input Voltage 100 650 mV Common-Mode Input Voltage 800 1575 mV Absolute Input Voltage 1.88 V ADC RESET2 ADC Start-Up Time After Reset6 Time to first DRDY, fast mode, decimation by 32 1.58 1.66 ms Minimum RESET Low Pulse Width tMCLK = 1/MCLK 2 × tMCLK LOGIC INPUTS See Table 2 for 1.8 V operation Input Voltage2 High, VINH 0.65 × IOVDD V Low, VINL 0.7 V Hysteresis2 0.04 0.09 V Leakage Current −10 +0.03 +10 µA RESET pin7 −10 +10 µA LOGIC OUTPUTS See Table 2 for 1.8 V operation Output Voltage2 High, VOH ISOURCE = 200 μA 0.8 × IOVDD V Low, VOL ISINK = 400 µA 0.4 V |
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Descrizione simile - AD7768-4BSTZ-RL |
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