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AD7124-8BCPZ-RL Scheda tecnica(PDF) 9 Page - Analog Devices |
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AD7124-8BCPZ-RL Scheda tecnica(HTML) 9 Page - Analog Devices |
9 / 91 page Data Sheet AD7124-8 Rev. B | Page 9 of 91 Parameter1 Min Typ Max Unit Test Conditions/Comments LOGIC OUTPUTS (INCLUDING CLK) Output Voltage2 High, VOH IOVDD − 0.35 V ISOURCE = 100 µA Low, VOL 0.4 V ISINK = 100 µA Floating State Leakage Current −1 +1 µA Floating State Output Capacitance 10 pF Data Output Coding Offset binary SYSTEM CALIBRATION2 Calibration Limit Full-Scale 1.05 × FS V Zero-Scale −1.05 × FS V Input Span 0.8 × FS 2.1 × FS V POWER SUPPLY VOLTAGES FOR ALL POWER MODES AVDD to AVSS Low Power Mode 2.7 3.6 V Mid Power Mode 2.7 3.6 V Full Power Mode 2.9 3.6 V IOVDD to GND 1.65 3.6 V AVSS to GND −1.8 0 +1.8 V IOVDD to AVSS 5.4 V POWER SUPPLY CURRENTS9, 11 IAVDD, External Reference Low Power Mode Gain = 12 125 135 µA All buffers off Gain = 1 IAVDD Increase per AIN Buffer2 15 20 µA Gain = 2 to 8 205 235 µA Gain = 16 to 128 235 280 µA IAVDD Increase per Reference Buffer2 10 15 µA All gains Mid Power Mode Gain = 12 150 165 µA All buffers off Gain = 1 IAVDD Increase per AIN Buffer2 30 35 µA Gain = 2 to 8 275 325 µA Gain = 16 to 128 330 405 µA IAVDD Increase per Reference Buffer2 20 30 µA All gains Full Power Mode Gain = 12 315 345 µA All buffers off Gain = 1 IAVDD Increase per AIN Buffer2 90 125 µA Gain = 2 to 8 660 790 µA Gain = 16 to 128 875 1100 µA IAVDD Increase per Reference Buffer2 85 110 µA All gains IAVDD Increase Due to Internal Reference2 50 65 µA Independent of power mode; the reference buffers are not required when using this reference Due to VBIAS2 15 20 µA Independent of power mode Due to Diagnostics2 4 5 µA IIOVDD Low Power Mode 20 35 µA Mid Power Mode 25 40 µA Full Power Mode 55 85 µA |
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