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DAC7551TDRNRQ1 Scheda tecnica(PDF) 6 Page - Texas Instruments |
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DAC7551TDRNRQ1 Scheda tecnica(HTML) 6 Page - Texas Instruments |
6 / 27 page SCLK SYNC SDIN D15 D14 D13 D12 D11 D1 D0 D15 t 8 t 4 t 3 t 2 t 1 t 7 t 6 t 5 D0 t 9 Input Word n Input Word n+1 Undefined D15 D14 D0 Input Word n t 10 SDO CLR DAC7551-Q1 SLAS767B – JUNE 2011 – REVISED MARCH 2015 www.ti.com 6.6 Timing Requirements (1) All specifications at –40°C to +105°C, VDD = 2.7 to 5.5 V, and RL = 2 kΩ to GND (unless otherwise noted). See Figure 1. MIN MAX UNIT VDD = 2.7 V to 3.6 V 20 t1 (2) SCLK cycle time ns VDD = 3.6 V to 5.5 V 20 VDD = 2.7 V to 3.6 V 6.5 t2 SCLK HIGH time ns VDD = 3.6 V to 5.5 V 6.5 VDD = 2.7 V to 3.6 V 6.5 t3 SCLK LOW time ns VDD = 3.6 V to 5.5 V 6.5 VDD = 2.7 V to 3.6 V 4 t4 SYNC falling edge to SCLK falling edge setup time ns VDD = 3.6 V to 5.5 V 4 VDD = 2.7 V to 3.6 V 3 t5 Data setup time ns VDD = 3.6 V to 5.5 V 3 VDD = 2.7 V to 3.6 V 3 t6 Data hold time ns VDD = 3.6 V to 5.5 V 3 VDD = 2.7 V to 3.6 V 0 t1 – 10 ns (3) t7 SCLK falling edge to SYNC rising edge ns VDD = 3.6 V to 5.5 V 0 t1 – 10 ns (3) VDD = 2.7 V to 3.6 V 20 t8 Minimum SYNC HIGH time ns VDD = 3.6 V to 5.5 V 20 VDD = 2.7 V to 3.6 V 10 t9 SCLK falling edge to SDO valid ns VDD = 3.6 V to 5.5 V 10 VDD = 2.7 V to 3.6 V 10 t10 CLR pulse width low ns VDD = 3.6 V to 5.5 V 10 (1) All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH) / 2. (2) Maximum SCLK frequency is 50 MHz at VDD = 2.7 to 5.5 V. (3) SCLK falling edge to SYNC rising edge time shold not exceed (t1 – 10 ns) to latch the correct data. Figure 1. Serial Write Operation Timing Diagram 6 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: DAC7551-Q1 |
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