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DAC128S085 Scheda tecnica(PDF) 4 Page - Texas Instruments |
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DAC128S085 Scheda tecnica(HTML) 4 Page - Texas Instruments |
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4 / 35 page  1 2 3 4 9 10 11 12 DAC128S085 VOUTA VOUTB VOUTC VOUTD VOUTG VOUTF VOUTH VOUTE DAC128S085 1 2 3 4 5 6 7 8 13 14 15 16 9 10 11 12 SCLK SYNC VOUTG VOUTF VOUTH VOUTE GND VREF2 VOUTA VA VOUTB VOUTC VOUTD VREF1 DIN DOUT DAC128S085 SNAS407H – AUGUST 2007 – REVISED APRIL 2015 www.ti.com 6 Pin Configuration and Functions RGH Package PW Package 16-Pin WQFN 16-Pin TSSOP (Top View) (Top View) Pin Functions PIN TYPE DESCRIPTION NAME TSSOP NO. WQFN NO. Serial Data Input. Data is clocked into the 16-bit shift register on the falling DIN 1 15 Digital Input edges of SCLK after the fall of SYNC. Serial Data Output. DOUT is utilized in daisy chain operation and is connected Digital DOUT 2 16 directly to a DIN pin on another DAC128S085. Data is not available at DOUT Output unless SYNC remains low for more than 16 SCLK cycles. GND 10 8 Ground Ground reference for all on-chip circuitry. Serial Clock Input. Data is clocked into the input shift register on the falling SCLK 16 14 Digital Input edges of this pin. Frame Synchronization Input. When this pin goes low, data is written into the DAC's input shift register on the falling edges of SCLK. After the 16th falling SYNC 15 13 Digital Input edge of SCLK, a rising edge of SYNC causes the DAC to be updated. If SYNC is brought high before the 15th falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. VA 7 5 Supply Power supply input. Must be decoupled to GND. Analog VOUTA 3 1 Channel A Analog Output Voltage. Output Analog VOUTB 4 2 Channel B Analog Output Voltage. Output Analog VOUTC 5 3 Channel C Analog Output Voltage. Output Analog VOUTD 6 4 Channel D Analog Output Voltage. Output Analog VOUTE 14 12 Channel E Analog Output Voltage. Output Analog VOUTF 13 11 Channel F Analog Output Voltage. Output Analog VOUTG 12 10 Channel G Analog Output Voltage. Output Analog VOUTH 11 9 Channel H Analog Output Voltage. Output Analog Unbuffered reference voltage shared by Channels A, B, C, and D. Must be VREF1 8 6 Input decoupled to GND. Analog Unbuffered reference voltage shared by Channels E, F, G, and H. Must be VREF2 9 7 Input decoupled to GND. Exposed die attach pad can be connected to ground or left floating. Soldering PAD — 17 Ground the pad to the PCB offers optimal thermal performance and enhances (WQFN only) package self-alignment during reflow. 4 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC128S085 |
Codice articolo simile - DAC128S085_15 |
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Descrizione simile - DAC128S085_15 |
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