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SN74CBTLV3253DGVR Scheda tecnica(PDF) 8 Page - Texas Instruments |
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SN74CBTLV3253DGVR Scheda tecnica(HTML) 8 Page - Texas Instruments |
8 / 27 page 2B1 1B1 2A 1A S0 S1 1OE 2OE 1B2 1B3 1B4 2B2 2B3 2B4 SW SW SW SW SW SW SW SW 7 9 14 2 1 15 6 5 4 3 10 11 12 13 SN74CBTLV3253 SCDS039I – DECEMBER 1997 – REVISED SEPTEMBER 2015 www.ti.com 8 Detailed Description 8.1 Overview The SN74CBTLV3253 device is a dual 1-of-4 high-speed FET multiplexer/demultiplexer. The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. The select (S0, S1) inputs control the data flow. The FET multiplexers and demultiplexers are disabled when the associated output-enable (OE) input is high. The SN74CBTLV3253 device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 8.2 Functional Block Diagram 8.3 Feature Description The SN74CBTLV3253 device is functionally equivalent to the QS3253 and has a 5- Ω switch connection between two ports It also has rail-to-rail switching on data I/O ports as well as Ioff supporting partial-power-down mode operation 8.4 Device Functional Modes Table 1 lists the functional modes of the SN74CBTLV3253. Table 1. Function Table (Each Multiplexer/Demultiplexer) INPUTS FUNCTION OE S1 S0 L L L A port = B1 port L L H A port = B2 port L H L A port = B3 port L H H A port = B4 port H X X Disconnect 8 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3253 |
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