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SM320VC33 Scheda tecnica(PDF) 9 Page - Texas Instruments |
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SM320VC33 Scheda tecnica(HTML) 9 Page - Texas Instruments |
9 / 53 page SM320VC33, SMJ320VC33 www.ti.com SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015 6.4 Phase-Locked Loop Characteristics Using EXTCLK or On-Chip Crystal Oscillator Timing Requirements see (1) (2) MIN MAX UNIT Fpllin Frequency range, PLL input 5(3) 15(3) MHz Fpllout Frequency range, PLL output 25(3) 75(3) MHz Ipll PLL current, CVDD supply 2(3) mA Ppll PLL power, CVDD supply 5(3) mW PLLdc PLL output duty cycle at H1 45%(3) 55%(3) PLLJ PLL output jitter, Fpllout = 25 MHz 400(3) ps PLLLOCK PLL lock time in input cycles 1000 cycles (1) Duty cycle is defined as 100 × t1 / (t1 + t2)% (2) To ensure clean internal clock references, the minimal low and high pulse durations must be maintained. At high frequencies, this may require a fast rise and fall time as well as a tightly controlled duty cycle. At lower frequencies, these requirements are less restrictive when in x1 and x0.5 modes. The PLL, however, must have an input duty cycle of between 40% and 60% for proper operation. (3) Not production tested 6.5 Circuit Parameters for On-Chip Crystal Oscillator Timing Requirements see Figure 2 (1) MIN TYP MAX UNIT VO Oscillator internal supply voltage CVDD V FO Fundamental mode frequency range 1(2) 20(2) MHz Vbias DC bias point (input threshold) 40(2) 50 60(2) %VO Rfbk Feedback resistance 100(2) 300 500(2) k Ω Rout Small signal ac output impedance 250(2) 500 1000(2) Ω Vxoutac The ac output voltage with test crystal(3) 85 %VO Vxinac The ac input voltage with test crystal (3) 85 %VO Vxoutl Vxin = Vxinh, Ixout = 0, FO = 0 (logic input) VSS – 0.1 (2) VSS + 0.3 (2) V Vxouth Vxin = Vxinl, Ixout = 0, FO = 0 (logic input) CVDD – 0.3 (2) CVDD + 0.1 (2) V Vinl When used for logic level input, oscillator enabled –0.3(2) 0.2 × VO (2) V Vinh When used for logic level input, oscillator enabled 0.8 × VO (2) DVDD + 0.3 (2) V Vxinh When used for logic level input, oscillator disabled 0.7 × DVDD DVDD + 0.3 V Cxout XOUT internal load capacitance 2(2) 3 5(2) pF Cxin XIN internal load capacitance 2(2) 3 5(2) pF td(XIN-H1) Delay time, XIN to H1 x1 and x0.5 modes 2 5.5 8 ns Iinl Input current, feedback enabled, Vil = 0 50(2) μA Iinh Input current, feedback enabled, Vil = Vih –50(2) μA (1) This circuit is intended for series resonant fundamental mode operation. (2) Not production tested (3) Signal amplitude is dependent on the crystal and load used. Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SM320VC33 SMJ320VC33 |
Codice articolo simile - SM320VC33_15 |
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Descrizione simile - SM320VC33_15 |
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