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AM3892CCYG135 Scheda tecnica(PDF) 2 Page - Texas Instruments

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Il numero della parte AM3892CCYG135
Spiegazioni elettronici  Sitara ARM Microprocessors
Download  313 Pages
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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AM3892CCYG135 Scheda tecnica(HTML) 2 Page - Texas Instruments

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AM3894
AM3892
SPRS681G – OCTOBER 2010 – REVISED MARCH 2015
www.ti.com
– 64 Independent DMA Channels and 8 Quick
– Two Clock Zones and Two Serial Data Pins
DMA (QDMA) Channels
– Supports TDM, I2S, and Similar Formats
• Seven 32-Bit General-Purpose Timers
• Real-Time Clock (RTC)
• One System Watchdog Timer
– One-Time or Periodic Interrupt Generation
• Three Configurable UART, IrDA, and CIR Modules
• Up to 64 General-Purpose I/O (GPIO) Pins
– UART0 with Modem Control Signals
• On-Chip ARM ROM Bootloader (RBL)
– Supports up to 3.6864 Mbps UART
• Power, Reset, and Clock Management
– SIR, MIR, FIR (4.0 MBAUD), and CIR
– SmartReflex™ Technology (Level 2)
• One 40-MHz Serial Peripheral Interface (SPI) with
– Seven Independent Core Power Domains
Four Chip Selects
– Clock Enable and Disable Control For
• SD and SDIO Serial Interface (1-Bit and 4-Bit)
Subsystems and Peripherals
• Dual Inter-Integrated Circuit ( I2C bus®) Ports
• IEEE 1149.1 (JTAG) and IEEE 1149.7 (cJTAG)
• Three Multichannel Audio Serial Ports (McASPs)
Compatible
– One Six-Serializer Transmit and Receive Port
• Via Channel™ Technology Enables use of
0.8-mm Design Rules
– Two Dual-Serializer Transmit and Receive Ports
• 40-nm CMOS Technology
– DIT-Capable For SDIF and PDIF (All Ports)
• 3.3-V Single-Ended LVCMOS I/Os (Except for
• Multichannel Buffered Serial Port (McBSP)
DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN
– Transmit and Receive Clocks up to 48 MHz
at 1.8 V)
2
Device Overview
Copyright © 2010–2015, Texas Instruments Incorporated
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Product Folder Links: AM3894 AM3892


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