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ADC10030CIVT Scheda tecnica(PDF) 3 Page - National Semiconductor (TI) |
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ADC10030CIVT Scheda tecnica(HTML) 3 Page - National Semiconductor (TI) |
3 / 17 page Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description 30 V IN Analog Input signal to be converted. Conversion range is V REF+ StoVREF− S. 31 V REF+ F Analog input that goes to the high side of the reference ladder of the ADC. This voltage should force V REF+ S to be in the range of 2.6V to 3.8V. 32 V REF+ S Analog output used to sense the voltage at the top of the ADC reference ladder. 2V REF− F Analog input that goes to the low side of the reference ladder of the ADC. This voltage should force V REF− S to be in the range of 1.7V to 2.8V. 1V REF− S Analog output used to sense the voltage at the bottom of the ADC reference ladder. 9 CLK Converter digital clock input. V IN is sampled on the falling edge of CLK input. 8PD Power Down input. When this pin is high, the converter is in the Power Down mode and the data output pins are in a high impedance state. 26 OE Output Enable pin. When this pin and the PD pin are low, the output data pins are active. When this pin or the PD pin is high, the data output pins are in a high impedance state. 14 thru 19 and 22 thru 25 D0–D9 Digital Output pins providing the 10-bit conversion results. D0 is the LSB, D9 is the MSB. Data is acquired on the falling edge of the CLK input and valid data is present 2.0 clock cycles plus t OD later. 3, 7, 28 V A Positive analog supply pins. These pins should be connected to a clean, quiet voltage source of +5V. V A and VD should have a common supply and be separately bypassed with 10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors. 5, 10 V D Positive digital supply pins. These pins should be connected to a clean, quiet voltage source of +5V. V A and VD should have a common supply and be separately bypassed with 10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors. www.national.com 3 |
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