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ADC08062CIWM Scheda tecnica(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Il numero della parte ADC08062CIWM
Spiegazioni elettronici  500 ns A/D Converter with S/H Function and Input Multiplexer
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Produttore elettronici  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC08062CIWM Scheda tecnica(HTML) 5 Page - National Semiconductor (TI)

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AC Electrical Characteristics (Continued)
The following specifications apply for V
+ = 5V, t
r = tf = 10 ns, VREF+ = 5V, VREF− = 0V unless otherwise specified. Bold-
face limits apply for T
A = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
Parameter
Condition
Typical
(Note 7)
Limits
(Note 8)
Units
(Limit)
tRDW
RD Width
Mode Pin to GND; (
Figure 5)
200
250
ns (min)
400
400
ns (max)
tCONV
WR -RD Mode Conversion Time
Mode Pin to V
+;(Figure 2)
500
560
ns (max)
(tWR +tRD +tACC1)
tCRD
RD Mode Conversion Time
Mode Pin to GND; (
Figure 1)
655
900
ns (max)
tACCO
Access Time (Delay from Falling
CL ≤ 100 pF
640
900
ns (max)
Edge of RD to Output Valid)
Mode Pin to GND; (
Figure 1)
tACC1
Access Time (Delay from
CL ≤ 10 pF
45
110
ns (max)
Falling Edge
CL = 100 pF
50
of RD to Output Valid)
Mode Pin to V
+,t
RD ≤ tINTL
(
Figure 2)
tACC2
Access Time (Delay from
CL ≤ 10 pF
25
55
ns (max)
Falling Edge
CL = 100 pF
30
of RD to Output Valid)
tRD > tINTL;(Figures 3, 4)
t0H
TRI-STATE® Control (Delay from
RL = 3kΩ,CL = 10 pF
30
60
ns (max)
Rising Edge of RD to HI-Z State)
t1H
TRI-STATE Control (Delay from
RL = 3kΩ,CL = 10 pF
30
60
ns (max)
Rising Edge of RD to HI-Z State)
tINTL
Delay from Rising Edge of
(
Figures 3, 4)
520
690
ns (max)
WR to Falling Edge of INT
Mode Pin = V
+,C
L = 50 pF
tINTH
Delay from Rising Edge of
CL = 50 pF; (Figures 1, 2, 3, 4)50
95
ns (max)
RD to Rising Edge of INT
2b, and 4 )
tINTH
Delay from Rising Edge of
CL = 50 pF; (Figure 4)45
95
ns (max)
WR to Rising Edge of INT
tRDY
Delay from CS to RDY
Mode Pin = 0V, CL = 50 pF,
25
45
ns (max)
RL = 3kΩ (Figure 1)
tID
Delay from INT to Output Valid
RL = 3kΩ,CL = 100 pF;
0
15
ns (max)
(
Figure 4)
tRI
Delay from RD to INT
Mode Pin = V
+,t
RD ≤ tINTL;
60
115
ns (max)
(
Figure 3)
tN
Time between End of RD
(
Figures 1, 2, 3, 4, 5)50
50
ns (min)
and Start of New Conversion
tAH
Channel Address Hold Time
(
Figures 1, 2, 3, 4, 5)10
60
ns (min)
tAS
Channel Address Setup Time
(
Figures 1, 2, 3, 4, 5)0
0
ns (max)
tCSS
CS Setup Time
(
Figures 1, 2, 3, 4, 5)0
0
ns (max)
tCSH
CS Hold Time
(
Figures 1, 2, 3, 4, 5)0
0
ns (min)
CVIN
Analog Input Capacitance
25
pF
COUT
Logic Output Capacitance
5
pF
CIN
Logic Input Capacitance
5
pF
DC Electrical Characteristics
The following specifications apply for V
+ = 5V unless otherwise specified. Boldface limits apply for T
A = TJ = TMIN to TMAX;
all other limits T
A = TJ = 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
Units
(Limit)
(Note 7)
(Note 8)
V
IH
Logic “1” Input Voltage
V
+ = 5.5V
Mode Pin
3.5
V (min)
ADC08062
CS, WR, RD, A0 Pins
2.2
V (min)
ADC08061
CS, WR, RD Pins
2.0
V (min)
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5


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