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ADC08061BIN Scheda tecnica(PDF) 11 Page - National Semiconductor (TI) |
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ADC08061BIN Scheda tecnica(HTML) 11 Page - National Semiconductor (TI) |
11 / 16 page Application Information (Continued) have a voltage drop of 1/256 of the total reference voltage (V REF+ −VREF−) across them. The remaining resistors make up the MSB Ladder. They are made up of eight groups of four resistors connected in series. Each MSB Ladder section has 1⁄8 of the total reference voltage across it. Within a given MSB Ladder section, each of the MSB resistors has 8/256, or 1/32 of the total reference voltage across it. Tap points are found between all of the resistors in both the MSB and LSB Ladders. Through the Comparator Multiplexer these tap points can be connected, in groups of eight, to the eight com- parators shown at the right of Figure 6. This function pro- vides the necessary reference voltages to the comparators during each flash conversion. The six comparators, seven-resistor string (estimator DAC), and Estimator Decoder at the left of Figure 6 form the Volt- age Estimator. The estimator DAC connected between V REF+ and VREF− generates the reference voltages for the six Voltage Estimator comparators. These comparators per- form a very low resolution A/D conversion to obtain an “esti- mate” of the input voltage. This estimate is then used to con- trol the Comparator Multiplexer, connecting the appropriate MSB Ladder section to the eight flash comparators. Only 14 comparators, six in the Voltage Estimator and eight in the flash converter, are needed to achieve the full eight-bit reso- lution, instead of 32 comparators that would be needed by traditional half-flash methods. A conversion begins with the Voltage Estimator comparing the analog input signal against the six tap voltages on the es- timator DAC. The estimator decoder then selects one of the groups of tap points along the MSB Ladder. These eight tap points are then connected to the eight flash comparators. For example, if the analog input signal applied to V IN is be- tween 0 and 3/16 of V REF (VREF = VREF+ −VREF−), the esti- mator decoder instructs the comparator multiplexer to select the eight tap points between 8/256 and 2/8 of V REF and con- nects them to the eight flash comparators. The first flash conversion is now performed, producing the five MSBs of data. The remaining three LSBs are generated next using the same eight comparators that were used for the first flash conversion. As determined by the results of the MSB flash, a voltage from the MSB Ladder equivalent to the magnitude of DS011086-18 FIGURE 6. Block Diagram of the ADC08061/2 Multi-Step Flash Architecture www.national.com 11 |
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