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9328FMQB Scheda tecnica(PDF) 3 Page - National Semiconductor (TI) |
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9328FMQB Scheda tecnica(HTML) 3 Page - National Semiconductor (TI) |
3 / 6 page Electrical Characteristics Over Recommended Operating Free Air Temperature Range (Unless Otherwise Noted) (Continued) Symbol Parameter Conditions Min Typ Max Units (Note 1) IOS Short Circuit VCC e Max MIL b 20 b 70 mA Output Current (Note 2) COMM b 20 b 70 ICC Supply Current VCC e Max 77 mA Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time Switching Characteristics VCC ea50V TA ea25 C (See Section 1 for waveforms and load configurations) CL e 15 pF Symbol Parameter RL e 400X Units Min Max fmax Maximum Shift Right Frequency 20 MHz tPLH Propagation Delay 20 ns tPHL CP to Q7 or Q735 tPHL Propagation Delay MR to Q7 50 ns Functional Description The two 8-bit shift registers have a common clock input (pin 9) and separate clock inputs (pins 10 and 7) The clocking of each register is controlled by the OR function of the sep- arate and the common clock input Each register is com- posed of eight clocked RS masterslave flip-flops and a number of gates The clock OR gate drives the eight clock inputs of the flip-flops in parallel When the two clock inputs (the separate and the common) to the OR gate are LOW the slave latches are steady but data can enter the master latches via the R and S input During the first LOW-to-HIGH transition of either or both simultaneously of the two clock inputs the data inputs (R and S) are inhibited so that a later change in input data will not affect the master then the now trapped information in the master is transferred to the slave When the transfer is complete both the master and the slave are steady as long as either or both clock inputs re- main HIGH During the HIGH-to-LOW transition of the last remaining HIGH clock input the transfer path from master to slave is inhibited first leaving the slave steady in its pres- ent state The data inputs (R and S) are enabled so that new data can enter the master Either of the clock inputs can be used as clock inhibit inputs by applying a logic HIGH signal Each 8-bit shift register has a 2-input multiplexer in front of the serial data input The two data inputs D0 and D1 are controlled by the data select input (S) following the Boolean expression Serial data in SD e SD0 a SD1 An asynchronous master reset is provided which when acti- vated by a LOW logic level will clear all 16 stages indepen- dently of any other input signal Shift Select Table INPUTS OUTPUT S D0D1Q7 (tn a 8) LL X L LH X H HX L L HX H H H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial n a 8 e indicates state after eight clock pulse 3 |
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